1. Technical Field
The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a polysilicon layer pattern as an etching mask.
2. Discussion of Related Art
A photoresist pattern is widely used as an etching mask in a pattern forming process because it simplifies the process and produces a pattern of desired shape and size. However, as design rules decrease to 100 nm or less, many problems emerge in semiconductor device manufacturing processes in which a photoresist pattern is used as an etching mask. For example, striation may occur in a material layer that remains after etching. Moreover, the etched material layer may be formed to an undesired pattern because there is a small margin for error in etching processes.
FIG. 1 illustrates a scanning electron microscopy (SEM) photograph of a semiconductor device on which a contact is formed by a self-aligned contact (SAC) method using a photoresist layer pattern as an etching mask with a 96 nm design rule. Referring to FIG. 1, many of the contacts have shapes that are different from the desired pattern shape, and furthermore, the pattern shape varies according to location on the semiconductor substrate.
To solve the above problems, a method of using a silicon nitride layer pattern or a polysilicon layer pattern as the etching mask has been developed. The occurrence of striation is prevented when a silicon nitride layer pattern or a polysilicon layer pattern is used as an etching mask (among the two layer patterns, the polysilicon layer is more preferable since it is deposited more easily than the silicon nitride layer). In addition, if an interlayer dielectric is etched with a dry etching method using a polysilicon layer pattern as the etching mask, the margin of error of the manufacturing process is greater than when the photoresist layer pattern is used as the etching mask.
FIGS. 2A through 2E are cross-sections illustrating a conventional method of forming a contact by a self-aligned contact (SAC) process using a polysilicon layer pattern as an etching mask.
Referring to FIG. 2A, a gate structure 110 is formed on a semiconductor substrate 100 using conventional manufacturing technology. The gate structure 110 includes a gate oxide layer 112, a gate conductive layer 114, a hard mask layer 116, and a sidewall spacer 118. Also, an etch stop layer 120 is formed on the semiconductor substrate 100 and the gate structure 110. Preferably, the etch stop layer 120 is formed of a material having a large etching selectivity with respect to an interlayer dielectric that will be formed on the etch stop layer 120. For instance, if the interlayer dielectric is a silicon oxide layer, the etch stop layer 120 may be formed of a silicon nitride layer.
Referring to FIG. 2B, the interlayer dielectric 130 is formed on the etch stop layer 120. Preferably, the interlayer dielectric 130 is formed of a silicon oxide material. A polysilicon layer pattern 140, which will be used as a hardmask, is formed on the interlayer dielectric 130.
Referring to FIG. 2C, the interlayer dielectric 130 is etched using the polysilicon layer pattern 140 as the etching mask to leave behind an interlayer dielectric pattern 130a. A material having a large etching selectivity with respect to the hard mask layer 116 and the sidewall spacer 118 is used as an etching gas or liquid when etching the interlayer dielectric 130. The section of the etch stop layer 120 exposed by the polysilicon layer pattern 140 and not in contact with the gate structure 110 is also etched. As a consequence, an etch stop layer pattern 120a remains on the gate structure 110 and a contact hole H that exposes the semiconductor substrate 100, is formed.
Next, a cleaning process to remove impurities including etching residues is performed. However, the interlayer dielectric pattern 130a is etched more than the polysilicon layer pattern 140 in the cleaning process such that the distance d1 between adjacent sections of the polysilicon layer 140 is less than the distance d2 between adjacent sections of the interlayer dielectric pattern 130a. This etching rate difference is inevitable when removing a native oxide layer or by-products that occur when etching. Consequently, as displayed in a dotted circle in FIG. 2C, the interlayer dielectric pattern 130a is etched more deeply than the polysilicon layer pattern 140a. 
The contact hole H is then filled with a conductive material such as doped polysilicon 150, resulting in the structure illustrated in FIG. 2D. Referring to FIG. 2D, a void or seam S may form in the doped polysilicon 150 filling the contact hole H. The void or seam S forms because the interlayer dielectric pattern 130a has a high etch selectivity with respect to the polysilicon layer pattern 140, causing the width of the interlayer dielectric pattern d2 to be larger than the width of the polysilicon layer pattern d1.
Referring to FIG. 2E, the polysilicon layer pattern 140 is removed until the interlayer dielectric pattern 130a is exposed, and the doped polysilicon 150 is etched at the same time. In this case, a dry etchback or a chemical mechanical polishing (CMP) process is utilized. As a result, a contact 150a including the void or seam S is formed in the interlayer dielectric pattern 130a. 
If the seam S exists in the contact 150a, contact resistance increases since the area of contact 150a is reduced. If by-products of etching or other impurities remain, the resistance further increases and the reliability of the semiconductor device may decrease.
An oxide buffing CMP process may be conducted to solve these problems. However, the oxide buffing CMP process cannot completely remove the seam S in the contact 150a and is expensive to implement.
Furthermore, when using the polysilicon layer pattern 140 as the etching mask, a process of removing the polysilicon layer pattern 140 is conducted only after filling the contact hole H. Accordingly, if the contact hole H is formed as shown in FIG. 2C, it cannot be determined whether the contact hole H is fully open when a substrate is in an in-line state using, for example, an SEM imaging process, because the polysilicon layer pattern 140 remains on the interlayer dielectric pattern 130a. Thus, destructive testing must be used.
Accordingly, there is a need for a method of manufacturing a semiconductor device using a polysilicon etching mask in which in-line testing can be used to determine whether a contact hole is fully open or not, and which prevents occurrence of seams inside a contact and reduces manufacturing costs.